1．Layout Dependent Effect-aware Leakage Current Reduction and Its Application to Low-power SAR-ADC，IEICE Transaction on Fundamentals of Electronics，Communication and Computer Sciences，2015-07-01，SCI收录，第一作者2．DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout，ACM Transactions on Design Automation of Electronic Systems （TODAES），2016-07-01，SCI收录，第一作者3．A New Sparse Design Framework for Broadband Power Amplifier Behavioral Modeling and Digital Predistortion，IEEJ TRANSACTIONS ON ELECTRICAL AND ELECTRONIC ENGINEERING，2014-06-01 ，SCI收录，第二作者4．Analog Circuit Synthesis with Constraint Generation of Layout Dependent Effects by Geometric Programming，IEICE Transaction on Fundamentals of Electronics，Communication and Computer Sciences，2013-12-01 ，SCI收录，第二作者5．A retargeting methodology of nano-watt CMOS reference circuit based on advanced compact MOSFET model，International Symposium on Circuits and Systems （ISCAS），2012-05-01，国际学术会议（EI收录），第一作者6．A comparator energy model considering shallow trench isolation stress by geometric programming，International Symposium on Quality Electronic Design (ISQED)，2013-03-01，国际学术会议（EI收录），第一作者7．Routability of Twisted Common-centroid Capacitor Array Under Signal Coupling Constraints， International Midwest Symposium on Circuits and Systems（MWSCAS），2016-10-19，国际学术会议（EI收录），第一作者8．A Novel Retargeting Methodology in Computer Aided Design of Nano-watt CMOS Reference Circuit based on Advanced Compact MOSFET Model，Journal of Computational Information Systems，2015-03-01，EI收录，第一作者9．A 9-bit 50MSps SAR ADC with Pre-charge VCM –based Double Input Range Algorithm，ACM international conference on Great lakes symposium on VLSI（GLSVLSI），2015-05-01，国际学术会议（EI收录），第一作者10．Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects，International Conference on Very Large Scale Integration (VLSI-SoC)，2013-11-01，国际学术会议（EI收录），第二作者
