个人简历
于北京大学获得学士（1997年），硕士（2000年），博士学位（2003年）。进入博士后工作站（2003年至2005年），留校任教（2005年至今）
研究领域
半导体物理 新兴器件设计和实现 有机器件和电路设计
近期论文
1.Liu L.K., Shi C., Zhang Y.B., and Sun L., Perspective analysis of tri gate germanium tunneling field-effect transistor with dopant segregation region at source/drain. Japanese Journal of Applied Physics, 2017. 56(4): 04CD18. 2.Zhang Y.B., Sun L., Xu H., and Han J.W., Simulation and comparative study of tunneling field effect transistors with dopant-segregated Schottky source/drain. Japanese Journal of Applied Physics, 2016. 55(4): 04ED09. 3.Zhang Y.B., Sun L., Xu H., Han J.W., Wang Y., and Zhang S.D., Comparative study of silicon nanowire transistors with triangular-shaped cross sections. Japanese Journal of Applied Physics, 2015. 54(4): 04DN01. 4.Xu H., Sun L., Zhang Y.B., Han J.W., Wang Y., and Zhang S.D., New concept of planar germanium MOSFET with stacked germanide layers at source/drain. Japanese Journal of Applied Physics, 2015. 54(4): 04DC13. 5.Han J.W., Sun L., Xu H., Zhang Y.B., Zhang S.D., and Wang Y., Impact of gate coupling and misalignment on performance of double-gate organic thin film transistors. Japanese Journal of Applied Physics, 2015. 54(4): 04DK04. 6.Zhang Y.B., Sun L., Xu H., Xia Y.Q., Wang Y., and Zhang S.D., Comparative study of dopant-segregated Schottky barrier germanium nanowire transistors. Japanese Journal of Applied Physics, 2014. 53(4): 04EN03. 7.Wang L.Y., Sun L., Han D.D., Wang Y., Chan M.S., and Zhang S.D., A hybrid a-Si and poly-Si TFTs technology for AMOLED pixel circuits. Journal of Display Technology, 2014. 10(4): 317-320. 8.Pu J., Sun L., and Han R.Q., Performance investigation on p-type Si-, Ge-, and Ge-Si core-shell nanowire Schottky barrier transistors. Japanese Journal of Applied Physics, 2011. 50(4): 04DN10. 9.Sun L., Li D.Y., Zhang S.D., Liu X.Y., Wang Y., and Han R.Q., A planar asymmetric Schottky barrier source/drain structure for nano-scale MOSFETs. Semiconductor Science and Technology, 2006. 21(5): 608-611. 10. Sun L., Li D.Y., Liu X.Y., and Han R.Q., Feasible approach to the fabrication of asymmetric Schottky barrier MOSFETs by using the spacer technique. Microelectronics Journal, 2006. 37(4): 332-335.
