个人简历

教育经历：\r
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◆ 2012-2016年，韩国科学技术院（KAIST）, 工学博士\r
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◆ 2006-2008年，韩国科学技术院（KAIST）, 工学硕士\r
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◆ 2002-2006年，北京邮电大学，工学学士\r
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工作经历：\r
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◆ 2017年至今， 浙江大学信息与电子工程学院、工程师学院 副教授\r
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◆ 2008-2017年，韩国LG集成电路研究所，历任 Junior R&D Research Engineer, R&D Research Engineer, Senior R&D Research Engineer, Principle R&D Research Engineer/项目主管

研究领域

高速GaN驱动器，高能量密度GaN DC-DC变换器，电源控制模型，新能源汽车电池管理系统BMS，无线能量传输，高性能放大器。""

近期论文

Kye-Seok Yoon; Hyun-Sik Kim; Wanyuan Qu; Young-Sub Yuk; Gyu-Hyeong Cho，“Fully Integrated Digitally Assisted Low-Dropout Regulator for a NAND Flash Memory System，” IEEE Transactions on Power Electronics, vol. 33, no. 1, pp. 388-406, Jan. 2018.\r
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Wanyuan Qu, S. Singh, Y. J. Lee, Y. S. Son, G. H. Cho, “Design-Oriented Analysis for Miller Compensation and Its Application to Multistage Amplifier Design,” IEEE J. Solid-State Circuits, vol. 52, no. 2, pp. 517–527, Feb. 2017.\r
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Wanyuan Qu, J. P. Im, H. S. Kim, and G. H. Cho, “A 0.9V 6.3μW multistage amplifier driving 500pF capacitive load with 1.34MHz GBW,” IEEE ISSCC Dig. Tech. Papers, 2014, pp. 290-291.\r
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Y. J. Lee, Wanyuan Qu, S. Singh, D. Y. Kim, K. H. Kim, S. H. Kim, J. J. Park and G. H Cho, “A 200-mA Digital Low Drop-out Regulator With Coarse-Fine Dual Loop in Mobile Application Processor,” IEEE J. Solid-State Circuits, vol. 52, no. 1, pp. 64–76, Jan. 2017.\r
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C. J. Jeong, Wanyuan Qu, Y. Sun, D. Y. Yoon, S. K. Han, and S. G. Lee, 'A 1.5-V, 140-uA CMOS Ultra-Low Power Common-Gate LNA ', IEEE Radio Frequency Integrated Circuits Symposium (RFIC), USA, June, 2011.