个人简历
熊晓明，EDA知名国际专家，广东工业大学“百人计划”特聘教授，华南理工大学客座教授。熊晓明博士主要擅长于产品架构、超大规模集成电路和片上芯片设计流程、多阶层集成电路设计方法、计算机辅助设计和计算几何学算法、平面布图规划、布局及布线、集成电路设计方法学等方面。早在1989年，熊晓明就与美国加州大学圣地亚哥分校著名教授陈中宽博士合作培养多名博士并多次在国内及美国著名大学举办IC设计和EDA专题讲座与学术讨论。熊晓明博士在美国工作二十多年期间主持并参与了多项研究项目，研发产品大多应用于美国国家半导体公司、美国IBM、日本NEC、美国LSI、美国英特尔等世界一流公司，产品获得用户的一致认可，代表世界最新技术及一流水平。被著名电子学家、EDA世界泰斗、美国工程学院院士、中国科学院外籍院士葛守仁教授誉为：开创中国EDA行业的理想领军人物。入职广东工业大学以来，在广东工业大学创建本科“2+2”IC班，建立Synopsys-广东工业大学EDA技术创新实验室和Cadence-广东工业大学集成电路设计技术创新实验室；在广州国家集成电路基地担任首席科学家，受广东省科技厅委托，参与广东省集成电路产业规划工作；在广州国家集成电路基地搭建EDA技术创新平台和硬件仿真平台，正在组建一支专业的集成电路产业技术服务团队。 在研项目包括：佛山市科技创新团队项目，高清晰图像和海量信息传输芯片设计两项广东省重大科技专项本科教学：《EDA技术与工具》、《片上系统设计技术》研究生教学：《片上系统设计方法学》
研究领域
"为集成电路和片上系统设计、集成电路计算机辅助设计和电子设计自动化。研究内容包括但不限于：纳电子学、计算机算法、图论、计算几何学。"
近期论文
Xiao Ming Xiong and Ernest S. Kuh, “The Scan Line Approach to Power and Ground Routing’” Digest of Technical Papers, IEEE International Conference on Computer-Aided Design, November 1986, pp. 6-9.Xiao-Ming Xiong and Ernest S. Kuh, “Nutcracker: an Efficient and Intelligent Channel Spacer,” Proc. of 24th Design Automation Conference, June 1987, pp. 298-304.Xiao-Ming Xiong, “Optimized One-Dimensional Compaction of Building-Block Layout,” Technical Report, Memo. No. UCB/ERL M87/45, May 1987.Wei-Ming Dai, Xiao-Ming Xiong et al, “BEAR: a New Building-Block Layout System,” Digest of Technical Papers, IEEE International Conference on Computer-Aided Design, November 1987, pp. 34-37.Xiao-Ming Xiong and Ernest S. Kuh, “The Constrained Via Minimization Problem for PCB and VLSI Design,” Proc. of 25th Design Automation Conference, June 1988, pp. 573-578.Xiao-Ming Xiong, “A New Algorithm for Topological Routing and Via Minimization,” Digest of Technical Papers, IEEE International Conference on Computer-Aided Design, November 1988, pp. 410-413.Xiao-Ming Xiong and Ernest S. Kuh, “A Unified Approach to the Via Minimization Problem,” IEEE Trans. on Circuits and Systems, Vol. 36, No. 2, February 1989, pp. 190-204.Xiao-Ming Xiong and Ernest S. Kuh, “Geometric Compaction of Building-Block Layout,” Proc. of Custom Integrated Circuits Conference, May 1989, pp. 17.6.1-17.6.4.Xiao-Ming Xiong, Dan Green, John Hardin and Lawrence Riedel, “Automatic Signal Net-Matching for VLSI Layout Design,” Proc. of IEEE International Conference on Computer Design, October 1989, pp. 524-527.Xiao-Ming Xiong, “Two-Dimensional Compaction for Placement Refinement,” Digest of Technical Papers, IEEE International Conference on Computer-Aided Design, November 1989, pp. 136-139.Xiao-Ming Xiong and Ernest S. Kuh, “Geometric Approach to VLSI Layout Compaction’” International Journal of Circuit Theory and Applications, Vol. 18, 1990, pp. 411-430.Xiao-Ming Xiong and Albert Chiu, “Efficient and Accurate Annotation of ECL Designs,” Proc. of the Third Physical Design Workshop, May 1991, Laurel Highlands, Pennsylvania.Xiao-Ming Xiong, “Routability Design for Sea-of-Cells,” Proc. of Fourth Annual IEEE International ASIC Conference and Exhibit, September 1991, pp. 14.3.1-14.3.4.J. W. Chung, R. Carragher, C. K. Cheng and X.-M. Xiong, “Performance Driven Routing Algorithm for Electronic Interconnects,” Proc. of International Workshop on Layout Synthesis, Research Triangle Park, North Carolina, May 1992, pp. 155-157.Xiao-Ming Xiong, John Hardin and Chung-Kuan Cheng, “PAS: A Stand Alone Placement Annotation System for High Speed Designs,” IEEE Custom Integrated Circuits Conf., May 1993, pp. 9.1.1-5.Robert J. Carragher, Chung-Kuan Cheng and Xiao-Ming Xiong, “The Net Matching Problem in High Performance Microelectronics Design,” Proc. of the Third International Conference on CAD and Computer Graphics, Beijing, China, August 1993, pp. 546-561.Xiao-Ming Xiong and Chung-Kuan Cheng, “Interconnect and Output Driver Modeling of High Speed Designs,” IEEE Int. Conf. on ASIC, September 1993, pp. 507-510.Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong and Ramamohan Paturi, “Solving the Net Matching Problem in High-Performance Chip Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 8, August 1996Xiao-Ming Xiong, Ben Mathew, and etc. “Design-for-Test-Aware Hierarchical Design Planning,” U.S. Patent No. 7,937,677, May 2011.Xiao-Ming Xiong, “Region Search Approach for Delay Routing and Signal Net Matching,” U.S. Patent No. 5,550,748, August 1996.
