个人简历

个人简介
2010年毕业于复旦大学微电子学与固体电子学专业，获理学学士学位，期间于美国加州大学戴维斯大学交流；2016年毕业于复旦大学微电子学院集成电路设计、测试与CAD专业，从事高性能数模混合集成电路设计研究，获理学博士学位。2016年至2018年于美国华盛顿大学电子工程系任博士后研究员，从事高能效数模混合集成电路与人工智能处理器芯片研究。2019年1月加入复旦大学工程与应用技术研究院任青年副研究员。
陈迟晓博士参与项目包括国家科技重大专项“面向IMT-Advanced宽带无线通信系统的数模混合集成电路研发”、科技部863计划（现更名为国家重点研发计划）“下一代光传输系统中的高速模数转换器/数模转换器芯片和关键技术研究”，国家自然科学基金面上项目“适用于20-80MHz的高频超声相控阵的MEMS压电换能器与高能效模数转换器研究”，上海市科委基础研究项目“类脑芯片与片上系统研究”等。陈迟晓博士已发表论文40余篇，授权专利10余项。 陈迟晓博士于2014年获得ISSCC STGA奖，并任IEEE JSSC/TCAS-I/TCAS-II/JETCAS审稿人。
陈迟晓博士也是知名半导体公众号“矽说”的共同创始人与主笔。

研究领域

人工智能处理器电路与体系结构，数模混合集成电路，面向智能硬件（控制器、传感器）的软硬件协同设计。"研究领域是集成电路芯片、人工智能和系统应用的交叉学科。"

近期论文

人工智能处理器 Deep Learning Processor
1.C. Chen, et al., “iFPNA: A Flexible and Efficient Deep Neural Network Accelerator with a Programmable Data Flow Engine in 28nm CMOS,” ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), Dresden, 2018, pp. 170-173.
2.C. Chen, et al., “OCEAN: An On-Chip Incremental-Learning Enhanced Artificial Neural Network Processor With Multiple Gated-Recurrent-Unit Accelerators,” in IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 3, pp. 519-530, Sept. 2018.
3.C. Chen et al., “OCEAN: An on-chip incremental-learning enhanced processor with gated recurrent neural network accelerators,” ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, Leuven, 2017, pp. 259-262.
数模混合集成电路 Analog and Mixed Signal Design
1.A. Wang, C. Chen and C. R. Shi, “A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 us Conversion Time”, Custom Integrated Circuit Conference (CICC 2019), Austin, TX, April 2019.
2.A. Wang, C. Chen and C. R. Shi, “Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 9, pp. 2284-2294, Sept. 2017.
3.C. Chen, et al., “An ARMA-Model-Based NTF Estimation on Continuous-Time Delta Sigma Modulator,” in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 62, no. 8, pp. 721-725, Aug. 2015.
4.C. Chen, et al., “A low-offset calibration-free comparator with a mismatch-suppressed dynamic preamplifier,” 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne VIC, 2014, pp. 2361-2364.
5.C. Chen, et al., “An 8-bit 100-MS/s Digital-to-Skew Converter with 200-ps range for time-interleaved sampling,” 2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS), Boise, ID, 2012, pp. 1100-1103.
6.B. Yu, C. Chen, et al., “A 14-bit 200-MS/s time-interleaved ADC with sample-time error detection and cancelation,” IEEE Asian Solid-State Circuits Conference 2011, Jeju, 2011, pp. 349-352.
软硬件协同设计 Hardware-Software Co-design
1.C. Chen, et al., “Exploring the Programmability for Deep Learning Processors: from Architecture to Tensorization,” 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC), San Francisco, CA, 2018, pp. 1-6.