研究领域

个人研究方向为数模混合集成电路和射频集成电路，主要从事模数转换器、数模转换器、频率综合器和高速数据传输接口等领域的研究

近期论文

[1] Jing Li, Shuangyi Wu, Yang Liu, Ning Ning, Qi Yu. A digital timing mismatch calibration technique in time-interleaved ADCs[J]. IEEE Transactions on Circuits and Systems II: Express Briefs, 2014, 61(7):486-490 [2] Jing Li, Ning Ning, Ling Du, Qi Yu, and Yang Liu. The impact of gate leakage current on PLL in 65 nm technology: analysis and optimization[J]. Journal of Semiconductor Technology and Science, 2012, 12(1):99-105 [3] Jing Li, Yang Liu, Shuangyi Wu, Ning Ning, Qi Yu. Digital background calibration for timing skew in time-interleaved ADC[J]. Journal of Circuits, Systems, and Computers, 2014, 23(8):1450117(1-13) [4] Jing Li, Yang Liu, Shuangyi Wu, Chang Yang, Ning Ning, Qi Yu. Design of a fast locking DLL with background timing skew calibration[J]. Nanoscience and Nanotechnology Letters, 2014, 6(12):1068-1074 [5] Jing Li, Ning Ning, Yong Hu, Kejun Wu. A Low-jitter Low-area PLL with Process-independent Bandwidth[C]. 2012 IEEE International Conference on Solid-State and Integrated Circuit Technology, Xi’an, 2012, 1-3 [6] Jing Li, Yang Liu, Shuangyi Wu, Ning Ning, Qi Yu. A background jitter optimization method for PLL based on time-to-digital converter[C]. 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, Chengdu, 2014 [7] Jing Li, Yang Liu, Hao Liu, Shuangyi Wu, Ning Ning and Qi Yu. A timing skew calibration scheme in Time-interleaved ADC[J]. Journal of Computer and Communications, 2013, 1:37-40 [8] Ning Ning, Zhiling Sui, Jing Li, Shuangyi Wu, Hua Chen, Shuangheng Xu, Qi Yu. Multiscaling coeffcients technique for gain error background calibration in pipelined ADC[J]. Journal of Circuits, Systems, and Computers, 2014, 23(3):1450034(1-12) [9] Ning Ning, Zhiling Sui, Jing Li, Shuangyi Wu, Hua Chen, Shuangheng Xu, Qi Yu. Multi scaling coefficients technique for noisy signal based gain error background calibration[C], 2012 IEEE International Conference on Electron Devices and Solid-State Circuits, Bangkok, 2012 [10] Ning Ning, Yong Hu, Jing Li, Chang Yang, Shuangyi Wu, Qi Yu. Design of a four phase 25% duty cycle DLL with calibration[C], 2013 IEEE International Conference on Electron Devices and Solid-State Circuits, Hongkong, 2013 [11] Qi Yu, Chang Yang, Jing Li, Shuangyi Wu, Ning Ning. Design of a high resolution multi-phase clock generato rbased on DLL[C], 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, Chengdu, 2014