研究领域

专利与技术转移共计: 1212. Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, "Single-Loop Linear-Exponential Multi-Bit Incremental Analog-to-Digital Converter", US Patent, No. 10,644,718 B1, , 05/05/2020 11. Pui In Mak, Seng-Pan U, R. P. Martins, "Two-Step Channel Selection for Wireless Transmitter Front-Ends", US Patent, Granted Number: 8,019,290, Sep. 13, 2011 10. Sai Weng Sin, He Gong Wei, Li Ding, Yan Zhu, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, "A Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption", US Patent, Granted Number: 8,427,355, Apr, 2013 9. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Delay Generator", US Patent, Granted Number: 8,441,295, May, 2013 8. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Cascade Analog to Digital Converting System", US Patent, Application Number: 13/198,856, Granted Number: 8,466,823, Jun, 2013 7. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, "Analog to Digital Converter Circuit", Taiwan Patent, Application Number: 100107757, Granted Number: 201242261, Mar, 2014 6. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Delay Generator", Taiwan Patent, Application Number: 100116148, Granted Number: 201246793, Mar, 2014 5. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "Sampling front-end for analog to digital converter", US patent, Application Number: 13/915,949, Granted Number: 8,947,283, Feb, 2015 4. Man-Chung Wong, Chi-Seng Lam, Yan-Zheng Yang, Wai-Hei Choi, Ning-Yi Dai, Ya-jie Wu, Chi-Kong Wong, Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, "Mixed signal controller", US patent, Granted, No. 9,692,232, Jun 2017 3. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "N-Bits Successive Approximation Register Analog-to-Digital Converting System", US Patent, Granted Number: 8,344,931, Jan, 2013 2. Pui In Mak, Seng-Pan U, R. P. Martins, "Switched Current-Resistor Programmable Gain Array for Low-Voltage Wireless LAN System and Method Using the Same", US Patent, Granted Number: 8,229,382, Jul, 2012 1. Pui In Mak, Seng-Pan U, R. P. Martins, "DC-Offset Canceled Programmable Gain Array for Low-Voltage Wireless LAN System and Method Using the Same", US Patent, Granted Number: 7,948,309, May, 2011

近期论文

期刊和杂志共计: 5959. Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, "A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS", IEEE Journal of Solid-State Circuits, Apr-2019. 58. Wang GuanCheng, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Nov-2018. 57. Yang Xiaofeng, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology", IEEE Transactions on Circuits and Systems I: Regular Papers, Jun-2018. 56. Chi Hang Chan, Yan Zhu, Zhang WaiHong, Seng-Pan U, R. P. Martins, "A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC with Background Offset Calibration", IEEE Journal of Solid-State Circuits, Mar-2018. 55. Yan Song, Chi Hang Chan, Yan Zhu, Li Geng, Seng-Pan U, R. P. Martins, "Passive Noise Shaping in SAR ADC With Improved Efficiency", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb-2018. 54. Weiwei Qin, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Quick and Cost-Efficient A/D Converter Static Characterization using Low-Precision Testing Signal", Microelectronics Journal - Elsevier, Feb-2018. 53. Mo Huang, Yan Lu, Seng-Pan U, R. P. Martins, "An Analog-Assisted Tri-Loop Digital Low-Dropout Regulator", IEEE Journal of Solid-State Circuits, Jan-2018. 52. Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek, Yan Zhu, Seng-Pan U, "A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Dec-2017. 51. Chi Hang Chan, Yan Zhu, Cheng Li, Zhang WaiHong, Ho Iok Meng, Lai Wei, Seng-Pan U, R. P. Martins, "60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration", IEEE Journal of Solid-State Circuits, Oct-2017. 50. Liang Qi, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, "A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH ΔΣ Modulator With Multirate Opamp Sharing", IEEE Transactions on Circuits and Systems I - Regular Papers, Oct-2017. 49. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC", in IEEE Transactions on Circuits and Systems I: Regular paper, Aug-2017. 48. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC", IEEE Transactions on Circuits and Systems I: Regular paper, Jul-2017. 47. Ziyang Luo, Yan Lu, Mo Huang, Junmin Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Sub-1V 78-nA Bandgap Reference with Curvature Compensation", Elsevier Microelectronics Journal, May-2017. 46. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, "Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Mar-2017. 45. Jiang DongYang, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Reconfigurable mismatch-free time-interleaved bandpass sigma–delta modulator for wireless communications", Electronics Letters, Mar-2017. 44. Yan Lu, Haojuan Dai, Mo Huang, Man-Kay Law, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Wide Input Range Dual-Path CMOS Rectifier for RF Energy Harvesting", IEEE Transactions on Circuits and Systems II, Feb-2017. 43. Yan Lu, Mo Huang, Lin Cheng, Wing-Hung Ki, Seng-Pan U, R. P. Martins, "A Dual-Output Wireless Power Transfer System with Active Rectifier and Three-Level Operation", IEEE Transactions on Power Electronics, Feb-2017. 42. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Boris Murmann, Seng-Pan U, R. P. Martins, "Metastablility in SAR ADCs", press in IEEE Transactions on CAS – Part II: Express Briefs, Feb-2017. 41. Yi-Wei Tan, Chi-Seng Lam, Sai Weng Sin, Man-Chung Wong, Seng-Pan U, R. P. Martins, "DCM operation analysis of 3-level boost converters", ”, IET Electronics Letters, Feb-2017. 40. Arshad Hussain, Sai Weng Sin, Chi Hang Chan, Seng-Pan U, Franco Maloberti, R. P. Martins, "Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan-2017. 39. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan-2017. 38. Mo Huang, Yan Lu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Wing-Hung Ki, "Limit Cycle Oscillation Reduction for Digital Low Dropout Regulators", IEEE Transactions on Circuits and Systems II, Sep-2016. 37. Yan Lu, Cheng Li, Yan Zhu, Mo Huang, Seng-Pan U, R. P. Martins, "A 312 ps Response-Time LDO with Enhanced Super Source Follower in 28 nm CMOS", Electronics Letters, Aug-2016. 36. Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 mW Flash ADC in 65 nm CMOS", in Journal of Semiconductor Technology and Science, Aug-2016. 35. Mo Huang, Yan Lu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Fully-Integrated Digital LDO with Coarse-Fine-Tuning and Burst-Mode Operation", IEEE Transactions on Circuits and Systems II, Jul-2016. 34. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "An 11b 450 MS/s 3-way Time-Interleaved Sub-ranging Pipelined-SAR ADC in 65nm CMOS", IEEE Journal of Solid-State Circuits, May-2016. 33. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC", IEEE Journal of Solid-State Circuits, Feb-2016. 32. Jianwei Lui, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan-2016. 31. Wen-Liang Zheng, Chi-Seng Lam, Wen-Ming Zheng, Sai Weng Sin, Ning-Yi Dai, Man-Chung Wong, Seng-Pan U, R. P. Martins, "DCM operation analysis of KY converter", IET Electronics Letters, Nov-2015. 30. Man-Chung Wong, Yan-Zheng Yang, Chi-Seng Lam, Wai-Hei Choi, Ning-Yi Dai, Ya-jie Wu, Chi-Kong Wong, Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, "Self-reconfiguration property of a mixed signal controller for improving power quality compensator during light loading", IEEE Transactions on Power Electronics, Oct-2015. 29. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs", IEEE Transactions on Circuits and Systems I: Regular Papers, Sep-2015. 28. Liang Qi, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Resolution-enhanced sturdy MASH delta–sigma modulator for wideband low-voltage applications", IET, ELECTRONICS LETTERS, Vol. 51, No. 14, pp. 1061–1063, Jul-2015. 27. Yan Zhu, Chi Hang Chan, Wong, S.-S., Seng-Pan U, R. P. Martins, "Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Jun-2015. 26. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Split-SAR ADCs: Improved Linearity with Power and Speed Optimization", ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb-2014. 25. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS", IEEE Journal of Solid-State Circuits, Sep-2013. 24. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC", IEEE Journal of Solid-State Circuits, Aug-2013. 23. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters", Analog Integrated Circuits and Signal Processing, Springer, Jul-2013. 22. Chenyan Cai, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Excess-Loop-Delay Compensation Technique for CT Delta Sigma Modulator with Hybrid Active-Passive Loop-Filters", Analog Integrated Circuits and Signal Processing, Vol. 76, Issue 1, May-2013. 21. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", IEEE Journal of Solid-State Circuits, Dec-2012. 20. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC", IEEE Journal of Solid-State Circuits, Nov-2012. 19. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC", IEEE Transactions on CAS – Part II: Express Briefs, Aug-2010. 18. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS", IEEE Journal of Solid-State Circuits, Jun-2010. 17. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs", Hindawi VLSI Design, Special Issue with "Selected Papers from the Midwest Symposium on Circuits and Systems, Apr-2010. 16. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 1.2-V 10-bit 60-360MS/s Time-Interleaved Pipelined ADC in 0.18um CMOS with Minimized Supply Headroom", IET Proceedings - Circuits, Devices and Systems, Jan-2010. 15. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS", IEEE Trans. on Circuits and System II – Express Briefs, Jan-2010. 14. Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 1-V 10b 40MS/s Pipelined ADC with Low-Voltage Circuit Techniques in 0.18um CMOS", 澳门机电工程专业协会(APEMEM)会刊(2007-2008), Apr-2009. 13. Sai Weng Sin, Seng-Pan U, R. P. Martins, "Generalized Circuit Techniques for Low-Voltage High-Speed Reset- and Switched-Opamps", IEEE Transactions on Circuits and Systems I - Regular Papers, Sep-2008. 12. Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, "Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch", IEEE Trans. on Circuits and Systems II – Express Briefs, Jul-2008. 11. Pui In Mak, Seng-Pan U, R. P. Martins, "On the Design of Programmable-Gain Amplifier with Built-in Compact DC-Offset Cancellers for Very Low-Voltage WLAN Systems", ", IEEE Transactions on Circuits and Systems – I: Regular Papers, Mar-2008. 10. Pui In Mak, Seng-Pan U, R. P. Martins, "An Experimental 1-V Flexible-IF CMOS Analogue-Baseband Chain for IEEE 802.11a/b/g WLAN Receivers", IET Proceedings - Circuits, Devices and Systems, Dec-2007. 9. Pui In Mak, Seng-Pan U, R. P. Martins, "Transceiver Architecture Selection - Review, State-of-the-Art Survey and Case Study", IEEE Circuits and Systems Magazine, Jun-2007. 8. Pui In Mak, Seng-Pan U, R. P. Martins, "Two-Step Channel Selection – A Novel Technique for Reconfigurable Multistandard Transceiver Front-Ends", IEEE Transactions on Circuits and Systems-I, Regular Paper, Jul-2005. 7. Seng-Pan U, Sai Weng Sin, R. P. Martins, "Exact Spectra Analysis of Sampled Signals with Jitter-Induced Nonuniformly Holding Effects", IEEE Transactions on Instrumentation and Measurement, Aug-2004. 6. Pui In Mak, Seng-Pan U, R. P. Martins, "Two-Step Channel Selection Technique by Programmable Digital-Double Quadrature Sampling for Complex Low-IF Receivers", IEE Electronics Letters, May-2003. 5. Seng-Pan U, R. P. Martins, J.E.Franca, "A 2.5-V 57-MHz 15-Tap SC Bandpass Interpolating Filter with 320-MHz Output for DDFS System in 0.35-µm CMOS", IEEE Journal of Solid-State Circuits, Feb-2002. 4. Seng-Pan U, R. P. Martins, J.E.Franca, "Improved Switched-Capacitor Interpolators with Reduced Sample-and-Hold Effects", IEEE Transactions on Circuits and Systems – II: Analog and Digital Signal Processing, Aug-2000. 3. Seng-Pan U, R. P. Martins, J.E.Franca, "Offset-& Gain-Compensated and Mismatch-Free SC Delay Circuit with Flexible Implementation", Offset-& Gain-Compensated and Mismatch-Free SC Delay Circuit with Flexible Implementation, Feb-1999. 2. Seng-Pan U, R. P. Martins, J.E.Franca, "Impulse Sampled FIR Interpolation with SC Active-Delayed Block Polyphase Structures", IEE Electronics Letters, Mar-1998. 1. Seng-Pan U, R. P. Martins, J.E.Franca, "Switched-Capacitor Interpolators Without the Input Sample-and-Hold Filtering Effect", IEE Electronics Letters, May-1996. 会议报告和简报共计: 176176. Wenning Jiang, Yan Zhu, Chi Hang Chan, Boris Murmann, Seng-Pan U, R. P. Martins, "A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler", 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), [Highlighted Paper], Nov-2018. 175. Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, "A 550μW 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS", Proc. IEEE Symposium on VLSI Circuits - VLSI 2018, , Jun-2018. 174. Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, "A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS", 2018 IEEE Symposium on VLSI Circuits, [Travel Grant Award] [Invited Special Issue in JSSC], Jun-2018. 173. Chi Hang Chan, Yan Zhu, Seng-Pan U, R. P. Martins, "A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC", forthcoming Proc. IEEE International Symposium on Circuits and Systems – ISCAS 2018, , May-2018. 172. Fangyu Mao, Yan Lu, Jie Lin, ChenChang Zhan, Seng-Pan U, R. P. Martins, "A Single-Stage Current-Mode Active Rectifier with Accurate Output-Current Regulation for IoT", forthcoming Proc. IEEE International Symposium on Circuits and Systems – ISCAS 2018, , May-2018. 171. Yuanqing Huang, Yan Lu, Franco Maloberti, Seng-Pan U, R. P. Martins, "A Dual-Loop Digital LDO Regulator with Asynchronous-Flash Binary Coarse Tuning", forthcoming Proc. IEEE International Symposium on Circuits and Systems – ISCAS 2018, , May-2018. 170. Fangyu Mao, Yan Lu, Seng-Pan U, R. P. Martins, "A 6.78 MHz active voltage doubler with near-optimal on/off delay compensation for wireless power transfer systems", International Symposium on VLSI Design, Automation and Test (VLSI-DAT), , Apr-2018. 169. Fangyu Mao, Yan Lu, Seng-Pan U, R. P. Martins, "A reconfigurable cross-connected wireless-power transceiver for bidirectional device-to-device charging with 78.1% total efficiency", 2018 IEEE International Solid - State Circuits Conference - (ISSCC), , Feb-2018. 168. Yang Xiaofeng, Yan Zhu, Chi Hang Chan, Wang GuanCheng, Seng-Pan U, "A 430frms 2.4GHz Ring-Oscillator PLL with Backend Discrete-Time Phase Noise Cancellation Achieving 240.5dB Jitter-FoM", IEEE International Solid-State Circuits Conference (ISSCC 2018), [Student Research Preview], Feb-2018. 167. Junmin Jiang, Yan Lu, Wing-Hung Ki, Philip K. T. Mok, Seng-Pan U, R. P. Martins, "A Dual-Output SC Converter with Dynamic Power Allocation for Multi-Core Application Processors", Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC,, pp. 285-286, Jan-2018. 166. Wei Wang, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 5.35 mW 10 MHz Bandwidth CT Third-Order ∆∑ Modulator with Single Opamp Achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS", IEEE Asian Solid-State Circuits Conference (A-SSCC), (highlighted paper and suggested to JSSC special issue), pp.285-288, Nov-2017. 165. U-Fat Chio, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, "A 5-bit 2 GS/s binary-search ADC with charge-steering comparators", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp221-224, Nov-2017. 164. Wang GuanCheng, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC", ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, Leuven, pp. 239-242., Sep-2017. 163. Xia Du, Chi-Seng Lam, Sai Weng Sin, Man-Kay Law, Franco Maloberti, Man-Chung Wong, Seng-Pan U, R. P. Martins, "A digital pwm controlled ky step-up converter based on frequency domain ΣΔ ADC", The 26th IEEE International Symposium on Industrial Electronics (ISIE 2017), pp.561-564, Jun-2017. 162. Mingqiang Guo, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Split-based time-interleaved ADC with digital background timing-skew calibration", 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME), , Jun-2017. 161. Mo Huang, Yan Lu, Seng-Pan U, R. P. Martins, "A Reconfigurable Bidirectional Wireless Power Transceiver with Maximum Current Charging Mode and 58.6% Battery-to-Battery Efficiency", IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), pp.376-378, Feb-2017. 160. Mo Huang, Yan Lu, Seng-Pan U, R. P. Martins, "An Output-Capacitor-Free Analog-Assisted Digital Low-Dropout Regulator with Tri-loop Control", IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), , Feb-2017. 159. Junmin Jiang, Yan Lu, Wing-Hung Ki, Seng-Pan U, R. P. Martins, "A Dual-Symmetrical-Output Switched-Capacitor Converter with Dynamic Power Cells and Minimized Cross Regulation for Application Processors in 28nm CMOS", IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), , Feb-2017. 158. Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Seng-Pan U, R. P. Martins, "A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration", IEEE International Solid-State Circuits Conference (ISSCC), pp. 282-284, Feb-2017. 157. Wei Li, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Mixed-Signal Sigma-Delta Interface circuit for Navigation System Applications", International Symposium on Integrated Circuits, , Dec-2016. 156. Yuan Ren, Sai Weng Sin, Chi-Seng Lam, Man-Chung Wong, Seng-Pan U, R. P. Martins, "A high DR multi-channel stage-shared hybrid sigma-delta modulator for integrated power electronics controller front-end", IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, Japan, Nov-2016. 155. Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Chon-Lam Lio, Seng-Pan U, R. P. Martins, "A 0.011mm2 60dB SNDR 100MS/s Reference Error Calibrated SAR ADC with 3pF Decoupling Capacitance for Reference Voltages", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 145-148 (highlighted paper and invited to JSSC special issue), Nov-2016. 154. Lei Qiu, Kai Tang, Yan Zhu, Liter Siek, Yuanjin Zheng, Seng-Pan U, "A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp: 77 – 80, Nov-2016. 153. Mo Huang, Yan Lu, Seng-Pan U, R. P. Martins, "A Digital LDO with Transient Enhancement and Limit Cycle Oscillation Reduction", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), , Oct-2016. 152. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, "Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching", IEEE ISCAS 2017, accepted, Oct-2016. 151. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction", IEEE European Solid-State Circuits Conference – ESSCIRC 2016, pp. 169-172, Sep-2016. 150. Biao Wang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A high resolution multi-bit incremental converter insensitive to DAC mismatch error", Ph.D Research in Micro-electronics & Electronics (PRIME), , Jun-2016. 149. Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation", IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015, pp.1-4, Nov-2015. 148. Mo Huang, Yan Lu, Xiao-ming Xiong, Seng-Pan U, R. P. Martins, "An All-Factor Modulation Bandwidth Extension Technique for Delta-Sigma PLL Transmitter", IEEE Region 10 Conference (TENCON), pp. 1-4. Professional Award, Nov-2015. 147. Wen-Ming Zheng, Chi-Seng Lam, Sai Weng Sin, Yan Lu, Man-Chung Wong, Seng-Pan U, R. P. Martins, "Capacitive floating level shifter: Modeling and design", IEEE Region 10 Conference (TENCON), Macau, China, pp. 1-6, Nov-2015. 146. Haojuan Dai, Yan Lu, Man-Kay Law, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Review and Design of the On-Chip Rectifiers for RF Energy Harvesting", IEEE International Wireless Symposium (IWS), pp. 1-4, Mar-2015. 145. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 Full-Calibration Integrated Pipelined-SAR ADC", International Solid State Circuits Conference (ISSCC), Student Research Previews, Feb-2015. 144. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS", Solid- State Circuits Conference - (ISSCC), (Pre-doctoral achievement awards),pp1-3, Feb-2015. 143. Yan Lu, Junmin Jiang, Wing-Hung Ki, C. Patrick Yue, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 123-Phase DC-DC Converter-Ring with Fast-DVS for Microprocessors", IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), pp. 364-365, Feb-2015. 142. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "An 11b 900 MS/s Time-Interleaved Sub-ranging Pipelined-SAR ADC", IEEE European Solid-State Circuit Conference – (ESSCIRC), pp.211-214, Sep-2014. 141. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 10.4-ENOB 120MS/s SAR ADC with DAC Linearity Calibration in 90nm CMOS", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 69-72, Nov-2013. 140. Li Ding, WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 13-bit 60M Split Pipelined ADC with Background Gain and Mismatch Error Calibration", IEEE Asian Solid-State Circuit Conference – (A-SSCC),, pp 77-80, Nov-2013. 139. Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Background Gain-Calibration Technique for Low Voltage Pipelined ADCs Based on Nonlinear Interpolation", IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS), pp 665-668, Aug-2013. 138. Yan Du, Tao He, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Continuous-Time VCO-Assisted VCO-Based Sigma Delta Modulator with 76.6dB SNDR and 10MHz BW", IEEE International Symposium on Circuits and Systems (ISCAS), pp 373-376, May-2013. 137. WenLan Wu, Yan Zhu, U-Fat Chio, Li Ding, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 0.6V 8B 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS", IEEE International Symposium on Circuits and Systems (ISCAS), pp 2239-2242, May-2013. 136. Yun Du, Tao He, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Continuous-Time VCO-Assisted VCO-Based ΣΔ Modulator with 76.6dB SNDR and 10MHz BW", in IEEE International Symposium on Circuits and Systems (ISCAS), , May-2013. 135. Yun Du, Tao He, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Robust NTF Zero Optimization Technique for Both Low and High OSRs Sigma-Delta Modulators", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp 29-32, Dec-2012. 134. Tao He, Yun Du, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A DT 0-2 MASH Modulator with VCO-Based Quantizer for Enhanced Linearity", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp 33-36, Dec-2012. 133. WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 10-bit SAR ADC With Two Redundant Decisions and Splitted-MSB-Cap DAC Array", IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), pp 268-271, Dec-2012. 132. Yun Du, Tao He, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A robust NTF Zero Optimization Technique for both Low and High OSRs Sigma-Delta Modulators", in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), , Dec-2012. 131. Tao He, Yun Du, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A DT 0–2 MASH ΣΔ Modulator with VCO-Based Quantizer for Enhanced Linearity", in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), , Dec-2012. 130. Zhijie Chen, Yang Jiang, ChenYan Cai, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 257-260, Nov-2012. 129. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Inter-Stage Gain Error Self-Calibration of a 31.5fJ 10b 470MS/s Pipelined-SAR ADC", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 153-156, Nov-2012. 128. Zhijie Chen, JIANG Yang, Chenyan Cai, He-Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application", in IEEE Asian Solid State Circuits Conference (A-SSCC), , Nov-2012. 127. Guohe Yin, He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A 0.024mm2 4.9 fJ 10-Bit 2MS/s SAR ADC in 65 nm CMOS", IEEE European Solid-State Circuits Conference – ESSCIRC 2012, pp 377-380, Sep-2012. 126. Rui Wang, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A 12-Bit 110MS/S 4-Stage Single-Opamp Pipelined SAR ADC with Ratio-Based GEC Technique", IEEE European Solid-State Circuits Conference – ESSCIRC 2012, pp 265-268, Sep-2012. 125. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators", IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2012, pp 1096-1099, Aug-2012. 124. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC", IEEE Custom Integrated Circuits Conference – CICC 2012, pp 1-4, Aug-2012. 123. Chenyan Cai, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators", in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), , Aug-2012. 122. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC", 2012 Symposium on VLSI Circuits Digest of Technical Papers, pp 90-91, Jun-2012. 121. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure", 2012 Symposium on VLSI Circuits Digest of Technical Papers, pp 86-87, Jun-2012. 120. Tao He, Yang Jiang, Yun Du, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 10MHz BW 78dB DR CT ΣΔ Modulator with Novel Switched High Linearity VCO-Based Quantizer", IEEE Int. Symposium on Circuits and Systems (ISCAS), pp 65-69, May-2012. 119. Tao He, JIANG Yang, Yun Du, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 10MHz BW 78dB DR CT ΣΔ Modulator with Novel Switched High Linearity VCO-Based Quantizer", in IEEE International Symposium on Circuits and Systems (ISCAS), , May-2012. 118. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 61-64, Nov-2011. 117. Si-Seng Wong, U-Fat Chio, He Gong Wei, Chi Hang Chan, Hou-Lon Choi, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 73-76, Nov-2011. 116. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 233-236, Nov-2011. 115. Seng-Pan U, Sai Weng Sin, Yan Zhu, U-Fat Chio, He Gong Wei, R. P. Martins, "Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs", Proc. of IEEE International Symposium on Radio-Frequency Integration Technology – RFIT’2011, pp. 173-176, Nov-2011. 114. Arshad Hussain, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Hybrid Loopfilter Sigma-Delta Modulator With NTF Zero Compensation", International SoC Design Conference – ISOCC, pp. 76-79, Nov-2011. 113. Bo Sun, U-Fat Chio, Chi-Seng Lam, Ning-Yi Dai, Man-Chung Wong, Chi-Kong Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A FPGA-Based Power Electronics Controller for Hybrid Active Power Filters", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), Macao, China, pp. 25-28, Oct-2011. 112. Yuan Fei, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture", Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimaAsia), pp. 1-4, Oct-2011. 111. Rui Wang, U-Fat Chio, Chi Hang Chan, Li Ding, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A time-efficient dither-injection scheme for pipelined SAR ADC", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 9-12, Oct-2011. 110. Arshad Hussain, Sai Weng Sin, Seng-Pan U, R. P. Martins, "NTF Zero Compensation Technique For Passive Sigma-Delta Modulator", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 82-85, Oct-2011. 109. U-Fat Chio, Chi Hang Chan, Hou-Lon Choi, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 7-bit 300-MS/s Subranging ADC with Embedded Threshold & Gain-Loss Calibration", ", IEEE European Solid-State Circuits Conference – ESSCIRC 2011, pp. 363-366, Sep-2011. 108. JIANG Yang, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Clock-Jitter Sensitivity Reduction in CT Sigma-Delta Modulators Using Voltage-Crossing Detection DAC", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011. 107. Zhijie Chen, Peng Zhang, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Zhihua Wang, "Noise Shaping Implementation in Two-Step/SAR ADC Architectures Based on Delayed Quantization Error", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011. 106. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time Sigma-Delta Modulators", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011. 105. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Multi-Merged-Switched Redundant Capacitive DACs for 2b/cycle SAR ADC", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011. 104. Tao He, Yun Du, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range", IEEE International Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011. 103. Peng Zhang, Zhijie Chen, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A Charge Pump Based Timing-Skew Calibration for Time-Interleaved ADC", ", IEEE Midwest Symposium on Circuits and Systems – MWSCAS, pp. 1-4, Aug-2011. 102. Tao He, Yun Du, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range", in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), , Aug-2011. 101. Chenyan Cai, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time ΣΔ Modulators", in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), , Aug-2011. 100. Bo Sun, Ning-Yi Dai, U-Fat Chio, Man-Chung Wong, Chi-Kong Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "FPGA-based Decoupled Double Synchronous Reference Frame PLL for Active Power Filters", 2011 6th IEEE Conference on Industrial Electronics and Applications (ICIEA), pp. 2145 – 2150, Jun-2011. 99. He Gong Wei, Chi Hang