个人简介

Academic QualificationsPh.D. in Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, China (2015)M.Sc. in Electrical and Electronics Engineering, Faculty of Science and Technology, University of Macau, China (2011)B.Sc. in Electrical and Computer Engineering, University of Washington (Seattle) ,United States (2008)Professional ExperienceState-Key Laboratory of Analog and Mixed-Signal VLSI (AMSV)Assistant Professor, AMSV, University of Macau (Apr. 2017 – Present)Research Assistant Professor, AMSV, University of Macau (Jan. 2016 – Mar. 2017)Post-doc Follow, AMSV, University of Macau (Aug. 2015 – Dec. 2015)OthersSpecial Scientist, Dept. of EEE, University of California (Mar. 2016 – July. 2016)Teaching ExperienceB.Sc. CoursesAnalog Integrated Circuit Design (ECEN3017)Advanced Topics in Electrical and Computer Engineering (ECEN8001)Design Project (ECEB420)M.Sc. CoursesIntroduction to Research (ECEN7001)Thesis (ECEN7999)

研究领域

Analog and mixed-signal CMOS integrated circuitsHigh speed Nyquist ADC and Wideband SDM (DT and CT)Low jitter Ring-VCO-based PLLPUF

专利与技术转移共计: 55. Zihao Zheng, Lai Wei, Chi Hang Chan, Jan Craninckx, Jorge Lagos Benites, "Pipelined analogue to digital converter", EUROPEAN (under review), EP 20157326.8, , 2020/02/14 4. Sai Weng Sin, He Gong Wei, Li Ding, Yan Zhu, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, "A Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption", US Patent, Granted Number: 8,427,355, Apr, 2013 3. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, "Analog to Digital Converter Circuit", Taiwan Patent, Application Number: 100107757, Granted Number: 201242261, Mar, 2014 2. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "Sampling front-end for analog to digital converter", US patent, Application Number: 13/915,949, Granted Number: 8,947,283, Feb, 2015 1. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "N-Bits Successive Approximation Register Analog-to-Digital Converting System", US Patent, Granted Number: 8,344,931, Jan, 2013

近期论文

期刊和杂志共计: 2929. Wei Wang, Chi Hang Chan, Yan Zhu, R. P. Martins, "A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization", IEEE Journal of Solid-State Circuits, Jun-2020. 28. Wenning Jiang, Yan Zhu, Chi Hang Chan, R. P. Martins, "A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier", IEEE Journal of Solid-State Circuits, Feb-2020. 27. Yan Song, Chi Hang Chan, Yan Zhu, R. P. Martins, "A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC", IEEE Journal of Solid-State Circuits, Feb-2020. 26. Xuewei Lei, Yan Zhu, Chi Hang Chan, R. P. Martins, "A 4-b 7µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation", IEEE Transactions on Circuits and Systems I: Regular Papers, Sep-2019. 25. Cheng Li, Chi Hang Chan, Yan Zhu, R. P. Martins, "Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC", IEEE Transactions on Circuits and Systems I: Regular Papers, Jan-2019. 24. Yan Zhu, Chi Hang Chan, Zi Hao Zheng, Cheng Li, Jianyu Zhong, R. P. Martins, "A 0.19 mm² 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS", IEEE Transactions on Circuits and Systems I: Regular Papers,, Nov-2018. 23. Wang GuanCheng, Cheng Li, Yan Zhu, Jianyu Zhong, Yan Lu, Chi Hang Chan, R. P. Martins, "Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC", IEEE Transactions on Circuits and Systems I: Regular Papers, Nov-2018. 22. Wang GuanCheng, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Nov-2018. 21. Wei Wang, Yan Zhu, Chi Hang Chan, R. P. Martins, "A 5.35-mW 10-MHz Single-Opamp Third-Order CTΔΣModulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS", IEEE Journal of Solid-State Circuits, Oct-2018. 20. Yang Xiaofeng, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology", IEEE Transactions on Circuits and Systems I: Regular Papers, Jun-2018. 19. Chi Hang Chan, Yan Zhu, Zhang WaiHong, Seng-Pan U, R. P. Martins, "A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC with Background Offset Calibration", IEEE Journal of Solid-State Circuits, Mar-2018. 18. Yan Song, Chi Hang Chan, Yan Zhu, Li Geng, Seng-Pan U, R. P. Martins, "Passive Noise Shaping in SAR ADC With Improved Efficiency", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb-2018. 17. Chi Hang Chan, Yan Zhu, Cheng Li, Zhang WaiHong, Ho Iok Meng, Lai Wei, Seng-Pan U, R. P. Martins, "60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration", IEEE Journal of Solid-State Circuits, Oct-2017. 16. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC", in IEEE Transactions on Circuits and Systems I: Regular paper, Aug-2017. 15. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC", IEEE Transactions on Circuits and Systems I: Regular paper, Jul-2017. 14. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, "Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Mar-2017. 13. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Boris Murmann, Seng-Pan U, R. P. Martins, "Metastablility in SAR ADCs", press in IEEE Transactions on CAS – Part II: Express Briefs, Feb-2017. 12. Arshad Hussain, Sai Weng Sin, Chi Hang Chan, Seng-Pan U, Franco Maloberti, R. P. Martins, "Active-Passive ΔΣ Modulator for High-Resolution and Low-Power Applications", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan-2017. 11. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations", in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan-2017. 10. Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 mW Flash ADC in 65 nm CMOS", in Journal of Semiconductor Technology and Science, Aug-2016. 9. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "An 11b 450 MS/s 3-way Time-Interleaved Sub-ranging Pipelined-SAR ADC in 65nm CMOS", IEEE Journal of Solid-State Circuits, May-2016. 8. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC", IEEE Journal of Solid-State Circuits, Feb-2016. 7. Jianwei Lui, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jan-2016. 6. Yan Zhu, Chi Hang Chan, Wong, S.-S., Seng-Pan U, R. P. Martins, "Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC", Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, Jun-2015. 5. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Split-SAR ADCs: Improved Linearity with Power and Speed Optimization", ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Feb-2014. 4. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS", IEEE Journal of Solid-State Circuits, Sep-2013. 3. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", IEEE Journal of Solid-State Circuits, Dec-2012. 2. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC", IEEE Journal of Solid-State Circuits, Nov-2012. 1. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS", IEEE Journal of Solid-State Circuits, Jun-2010. 会议报告和简报共计: 4242. Kai Xing, Lei Wang, Yan Zhu, Chi Hang Chan, R. P. Martins, "A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SABELD-Merged Integrator and 3-Stage Opamp", 2020 Symposia on VLSI Technology and Circuits, , Jun-2020. 41. Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi Hang Chan, Jan Craninckx, R. P. Martins, "A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation", IEEE International Solid-State Circuits Conference (ISSCC), pp. 254-256, Feb-2020. 40. Yan Song, Yan Zhu, Chi Hang Chan, R. P. Martins, "A 2.56mW 40MHz-Bandwidth 75dB-SNDR PartialInterleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration", IEEE International Solid-State Circuits Conference (ISSCC), pp.164-166, Feb-2020. 39. Minglei Zhang, Yan Zhu, Chi Hang Chan, R. P. Martins, "A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input", IEEE International Solid-State Circuits Conference (ISSCC), pp. 252-254, Feb-2020. 38. Yan Song, Yan Zhu, Chi Hang Chan, R. P. Martins, "9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration", 2020 IEEE International Solid- State Circuits Conference - (ISSCC), pp. 164-166, Feb-2020. 37. Minglei Zhang, Yan Zhu, Chi Hang Chan, R. P. Martins, "16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input", 2020 IEEE International Solid- State Circuits Conference - (ISSCC), pp. 252-254., Feb-2020. 36. Wenning Jiang, Yan Zhu, Minglei Zhang, Chi Hang Chan, R. P. Martins, "A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier", IEEE International Solid-State Circuits Conference (ISSCC 2019, pp.60-62, Feb-2019. 35. Minglei Zhang, Chi Hang Chan, Yan Zhu, R. P. Martins, "A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques", IEEE International Solid-State Circuits Conference (ISSCC 2019), pp.66-68, Feb-2019. 34. Wei Wang, Chi Hang Chan, Yan Zhu, R. P. Martins, "A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ", IEEE International Solid-State Circuits Conference (ISSCC 2019), , Feb-2019. 33. Wenning Jiang, Yan Zhu, Chi Hang Chan, Boris Murmann, Seng-Pan U, R. P. Martins, "A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler", 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), [Highlighted Paper], Nov-2018. 32. Chi Hang Chan, Yan Zhu, Zihao Zheng, R. P. Martins, "A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end", ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC), , Sep-2018. 31. Yan Song, Yan Zhu, Chi Hang Chan, Li Geng, R. P. Martins, "A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure", Proc. IEEE Symposium on VLSI Circuits - VLSI 2018, , Jun-2018. 30. Chi Hang Chan, Yan Zhu, Seng-Pan U, R. P. Martins, "A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC", forthcoming Proc. IEEE International Symposium on Circuits and Systems – ISCAS 2018, , May-2018. 29. Yang Xiaofeng, Yan Zhu, Chi Hang Chan, Wang GuanCheng, Seng-Pan U, "A 430frms 2.4GHz Ring-Oscillator PLL with Backend Discrete-Time Phase Noise Cancellation Achieving 240.5dB Jitter-FoM", IEEE International Solid-State Circuits Conference (ISSCC 2018), [Student Research Preview], Feb-2018. 28. Wei Wang, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 5.35 mW 10 MHz Bandwidth CT Third-Order ∆∑ Modulator with Single Opamp Achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS", IEEE Asian Solid-State Circuits Conference (A-SSCC), (highlighted paper and suggested to JSSC special issue), pp.285-288, Nov-2017. 27. Wang GuanCheng, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC", ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference, Leuven, pp. 239-242., Sep-2017. 26. Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Seng-Pan U, R. P. Martins, "A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration", IEEE International Solid-State Circuits Conference (ISSCC), pp. 282-284, Feb-2017. 25. Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Chon-Lam Lio, Seng-Pan U, R. P. Martins, "A 0.011mm2 60dB SNDR 100MS/s Reference Error Calibrated SAR ADC with 3pF Decoupling Capacitance for Reference Voltages", IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 145-148 (highlighted paper and invited to JSSC special issue), Nov-2016. 24. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, "Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching", IEEE ISCAS 2017, accepted, Oct-2016. 23. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction", IEEE European Solid-State Circuits Conference – ESSCIRC 2016, pp. 169-172, Sep-2016. 22. Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation", IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015, pp.1-4, Nov-2015. 21. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 12b 180MS/s 0.068mm2 Full-Calibration Integrated Pipelined-SAR ADC", International Solid State Circuits Conference (ISSCC), Student Research Previews, Feb-2015. 20. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS", Solid- State Circuits Conference - (ISSCC), (Pre-doctoral achievement awards),pp1-3, Feb-2015. 19. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "An 11b 900 MS/s Time-Interleaved Sub-ranging Pipelined-SAR ADC", IEEE European Solid-State Circuit Conference – (ESSCIRC), pp.211-214, Sep-2014. 18. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, "A 10.4-ENOB 120MS/s SAR ADC with DAC Linearity Calibration in 90nm CMOS", IEEE Asian Solid-State Circuit Conference – (A-SSCC), pp 69-72, Nov-2013. 17. WenLan Wu, Yan Zhu, U-Fat Chio, Li Ding, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 0.6V 8B 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS", IEEE International Symposium on Circuits and Systems (ISCAS), pp 2239-2242, May-2013. 16. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC", 2012 Symposium on VLSI Circuits Digest of Technical Papers, pp 90-91, Jun-2012. 15. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure", 2012 Symposium on VLSI Circuits Digest of Technical Papers, pp 86-87, Jun-2012. 14. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 61-64, Nov-2011. 13. Si-Seng Wong, U-Fat Chio, He Gong Wei, Chi Hang Chan, Hou-Lon Choi, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 73-76, Nov-2011. 12. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS", Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic"), pp. 233-236, Nov-2011. 11. Rui Wang, U-Fat Chio, Chi Hang Chan, Li Ding, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, "A time-efficient dither-injection scheme for pipelined SAR ADC", IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia), pp. 9-12, Oct-2011. 10. U-Fat Chio, Chi Hang Chan, Hou-Lon Choi, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A 7-bit 300-MS/s Subranging ADC with Embedded Threshold & Gain-Loss Calibration", ", IEEE European Solid-State Circuits Conference – ESSCIRC 2011, pp. 363-366, Sep-2011. 9. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, "A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS", IEEE International Solid-State Circuit Conference (ISSCC),, pp. 188-189, Feb-2011. 8. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, "An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H", in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010, pp. 218-221, Sep-2010. 7. Si-Seng Wong, U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Power Effective 5-bit 600 MS/s Binary-Search ADC with Simplified Switching", in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 29-32, Aug-2010. 6. Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Threshold-Embedded Offset Calibration Technique for Inverter-Based Flash ADCs", in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 489-492, Aug-2010. 5. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Parasitics Nonlinearity Cancellation Technique for Split DAC Architecture by Using Capacitive Charge-Pump", IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010, pp. 889-892, Aug-2010. 4. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Voltage Feedback Charge Compensation Technique for Split DAC Architecture in SAR ADCs", IEEE International Symposium on Circuits and Systems – ISCAS 2010, pp. 607-611, May-2010. 3. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, "A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator", in Proc. of 2009 International SoC Design Conference (ISOCC), pp. 392-395, Nov-2009. 2. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Si-Seng Wong, "Parasitic Calibration by Two-Step Ratio Approaching Techinque for Split Capacitor Array SAR ADCs", in Proc. of 2009 International SoC Design Conference (ISOCC), pp. 333-336, Nov-2009. 1. U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Si-Seng Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, "Comparator-Based Successive Folding ADC", IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia), pp. 117-120, Jan-2009.