个人简介

Yong Chen received the B.Eng. degree in electronic and information engineering, Communication University of China (CUC), Beijing, China, in 2005, and the Ph.D. in Engineering degree in microelectronics and solid-state electronics, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, China, in 2010. From 2010 to 2013, He worked as Post-Doctoral Researcher in Institute of Microelectronics, Tsinghua University, Beijing, China. From 2013 to 2016, he was Research Fellow responsible for high-speed (40+Gb/s) wireline communication and Low Energy Electronic Systems (LEES) project under the Singapore-MIT Alliance for Research and Technology (SMART) on RF CMOS transceiver in VIRTUS/EEE, Nanyang Technological University, Singapore. He is now an Assistant Professor of the State Key Laboratory of Analog and Mixed-Signal VLSI (AMSV) of University of Macau, Macao, China, since March 2016. His research interests include analog/biomedical detection and RF integrated circuit, mm-wave system and circuit, high-speed on-chip and chip-to-chip Electrical/Optical InterconnectsAcademic QualificationsPh.D. in Microelectronics and Solid-State Electronics, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), China (2010)B.S. in Electronic and Information Engineering, Communication University of China, China (2005)Professional ExperienceInstitute of MicroelectronicsAssistant Professor, Institute of Microelectronics (IME), University of Macau (Apr. 2019 – Present)State-Key Laboratory of Analog and Mixed-Signal VLSIAssistant Professor, State-Key Lab. of Analog and Mixed-Signal VLSI (AMSV), University of Macau (Mar. 2016 – Present)OthersResearch Fellow in Nanyang Technological University, Singapore (Oct. 2013 – Feb. 2016)Post-doctoral in Institute of Microelectronics, Tsinghua University, Beijing, China (Jul. 2010 – Sep. 2013)

近期论文

期刊和杂志共计: 2222. Haohong Yu, Yong Chen, Chirn Chye Boon, Pui In Mak, R. P. Martins, "A 0.096-mm2 1-to-20-GHz Triple-Path Noise-Cancelling Common-Gate Common-Source LNA with Complementary pMOS-nMOS Configuration", IEEE Transactions on Microwave Theory and Techniques, Jan-2020. 21. Zunsong Yang, Yong Chen, Shiheng Yang, Pui In Mak, R. P. Martins, "A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector", IEEE Access, Jan-2020. 20. Yong Chen, Pui In Mak, Zunsong Yang, Chirn Chye Boon, R. P. Martins, "A 0.0071-mm² 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis", IEEE Transactions on Circuits and Systems I: Regular Paper, Oct-2019. 19. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, "A 0.0018-mm2 153%-Locking-Range CML-Based Divider-by-2 with Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell", IEEE Transactions on Circuits and Systems I: Regular Papers, Sep-2019. 18. Xinyi Ge, Yong Chen, Xiaoteng Zhao, Pui In Mak, R. P. Martins, "Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jun-2019. 17. Yong Chen, Zunsong Yang, Xiaoteng Zhao, Yunbo Huang, "A 6.5x7 µm2 0.98-to-1.5 mW Non-Self-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4 to 44 GHz)", IEEE Solid-State Circuits Letters, May-2019. 16. Haohong Yu, Yong Chen, Chirn Chye Boon, Chenyang Li, Pui In Mak, R. P. Martins, "A 0.044-mm2 0.5-to-7-GHz resistor-plus-source-follower-feedback noise-cancelling LNA achieving a flat NF of 3.3±0.45 dB", IEEE Transactions on Circuits and Systems - II, Jan-2019. 15. Lingshan Kong, Yong Chen, Chirn Chye Boon, Pui In Mak, R. P. Martins, "A wideband inductorless dB-linear automatic-gain control amplifier using a single-branch negative exponential generator for wireline applications", IEEE Transactions on Circuits and Systems - I, Oct-2018. 14. Yong Chen, Pui In Mak, Chirn Chye Boon, R. P. Martins, "A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin", IEEE Transactions on Circuits and Systems - I, Sep-2018. 13. Hao Guo, Yong Chen, Pui In Mak, R. P. Martins, "A 0.083-mm2 25.2-to-29.5 GHz Multi-LC-Tank Class-F234 VCO with a 189.6-dBc/Hz FOM", IEEE Solid-State Circuits Letters, Apr-2018. 12. Yong Chen, Pui In Mak, Haohong Yu, Chirn Chye Boon, R. P. Martins, "An Area-Efficient and Tunable Bandwidth-Extension Technique for a Wideband CMOS Amplifier Handling 50+ Gb/s Signaling", IEEE Transactions on Microwave Theory and Techniques, Dec-2017. 11. Yong Chen, Pui In Mak, Chirn Chye Boon, R. P. Martins, "A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS", IEEE Microwave and Wireless Components Letters, Sep-2017. 10. Yong Chen, Pui In Mak, Yan Wang, "A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links", IEEE Transactions on Very Large Scale Integration Systems, May-2015. 9. Yong Chen, Pui In Mak, Li Zhang, Yan Wang, "A 0.002-mm2 6.4-mW 10-Gb/s Full-Rate Direct DFE Receiver with 59.6% Horizontal Eye Opening at 10-12 BER under 23.3-dB Channel Loss at Nyquist", IEEE Transactions on Microwave Theory and Techniques, Dec-2014. 8. Yong Chen, Pui In Mak, Stefano D'Amico, Li Zhang, He Qian, Yan Wang, "A Single-Branch Third-Order Pole–Zero Low-Pass Filter With 0.014-mm2 Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth–Power Scalability", IEEE Transactions on Circuits and Systems – II, Nov-2013. 7. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, "0.013 mm2, kHz-to-GHz-bandwidth, thirdorder all-pole lowpass filter with 0.52-to- 1.11 pW/pole/Hz efficiency", IET Electronics Letters, Oct-2013. 6. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, "Pre-Emphasis Transmitter (0.007mm2, 8Gbit/s, 0-14dB) with Improved Data Zero-Crossing Accuracy in 65nm CMOS", IET Electronics Letters, Jul-2013. 5. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, "A 0.0012mm2, 8mW, Single-to-Differential Converter with <1.1% Data Cross Error and <3.4ps RMS Jitter up to 14Gb/s Data Rate", IET Electronics Letters, May-2013. 4. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, "A Fifth-Order 20-MHz Transistorized- -Ladder LPF With 58.2-dB SFDR, 68- Efficiency, and 0.13- Die Size in 90-nm CMOS", IEEE Transactions on Circuits and Systems – II, Jan-2013. 3. Yong Chen, Pui In Mak, L. Zhang, Y. Wang, "A 0.07mm2, 2mW, 75MHz-IF, 4th-Order BPF Using a Source-Follower-Based Resonator in 90nm CMOS", IET Electronics Letters, May-2012. 2. Yong Chen, Pui In Mak, Yumei Zhou, "Self-Tracking Charge Pump for Fast-Locking PLL", IET Electronics Letters, May-2010. 1. Yong Chen, Pui In Mak, Yumei Zhou, "Mixed-Integrator Biquad for Continuous-Time Filters", IET Electronics Letters, Apr-2010. 会议报告和简报共计: 99. Hao Guo, Yong Chen, Pui In Mak, R. P. Martins, "A 0.082mm2 24.5-to-28.3GHz Multi-LC-Tank Fully-Differential VCO Using Two Separate Single-Turn Inductors and a 1D-Tuning Capacitor Achieving 189.4dBc/Hz FOM and 200±50kHz 1/f3 PN Corner", IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, , Jun-2020. 8. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, "A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS", IEEE Custom Integrated Circuits Conference (CICC), , Mar-2020. 7. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, "A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS", IEEE Asia Pacific Conference on Circuits and Systems, , Nov-2019. 6. Zunsong Yang, Yong Chen, Shiheng Yang, Pui In Mak, R. P. Martins, "A 25.4-to-29.5GHz 10.2mW Isolated-Sub-Sampling PLL (iSS-PLL) Achieving -252.9dB Jitter-power FOM and -63dBc Reference Spur", IEEE International Solid-State Circuits Conference (ISSCC), pp. 270-272, Feb-2019. 5. Hao Guo, Yong Chen, Pui In Mak, R. P. Martins, "A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6-dBc/Hz FOM and 130kHz 1/f3 PN Corner", IEEE International Solid-State Circuits Conference (ISSCC), pp. 410-412, Feb-2019. 4. Yong Chen, Pui In Mak, Jiale Yang, Ruifeng Yue, Yan Wang, "Comparator with Built-in Reference Voltage Generation and Split-ROM Encoder for a High-Speed Flash ADC", International Symposium on Signals, Circuits and Systems (ISSCS), pp. 1-4, Jul-2015. 3. Yong Chen, Pui In Mak, Yumei Zhou, Hao Ju, Li Zhang, He Qian, Yan Wang, Zhiping Yu, "A 6-bit 1.3-GS/s Flash ADC using a Gain-Compensated THA and an Offset-Averaging Preamplifier Array", in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-4, May-2011. 2. Yong Chen, Pui In Mak, Yumei Zhou, Hao Ju, Li Zhang, He Qian, Yan Wang, Zhiping Yu, "A Fast Lock-in PLL Using a Quadratic V-I Self-Tracking Charge Pump and a Replica-Biased Ring VCO", IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1872-1875, May-2011. 1. Yong Chen, Pui In Mak, Yumei Zhou, "Source-follower-based bi-quad cell for continuous-time zero-pole type filters", of IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3629-3632, May-2010.